WSA 0338 – A9146M4
A9146M4 is a high performance and low cost SoC. It integrates M4F micro controller, 512KBytes flash memory, 80KBytes SRAM compatible controller and various powerful functions.
A9146M4’s RF is a monolithic low-IF architecture CMOS FSK/GFSK TRX for wireless applications in the 169/315/433/470/868/ 915MHz ISM bands. This device is especially suitable for battery-powered application and the 470MHz ~ 510MHz wireless AMR (Auto Meter Reading) in China and 169.4MHz/433.8MHz/868.3MHz wireless M-bus in Europe. For Wi-SUN and IEEE 802.15.4g applications, A9146M4 also built in HW 802.15.4g packet handling and HW-accelerated IEEE 802.15.4 compliant MAC features.
The RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 61Hz for 433/470 MHz band. The VCO frequency operates at the wanted radio frequency to cover all RF band.
A9146M4’s RF control registers are accessed via 3-wire or 4-wire SPI interface including TX/RF FIFO, VCO frequency, and chip calibration procedures. Another one, via SPI as well, is the unique Strobe Command, A9146M4’s RF can be controlled from power saving mode (deep sleep, sleep, idle, standby), PLL mode, TX mode and RX mode. In addition to SPI, the digital connections between A9146M4’s RF and A9146M4’s MCU are GIO1 and GIO2 (multi-function GPIO) to indicate A9146M4’s RF status so that MCU could use either polling or interrupt for radio control.
For packet handling, A9146M4’s RF supports direct mode and FIFO mode. In direct mode, MCU or Encoder shall deliver the defined packet (preamble + sync word + payload) to GIO1 or GIO2/TXD pin. Then, in RX mode, MCU or Decoder can receive the coming packet (preamble + sync word + payload) in bit sequence from GIO1 or GIO2/RXD pin.
In FIFO mode, preamble is self-generated by A9146M4’s RF. User just needs to assign the sync word to this device by ID R/W command via SPI. For payload, the built-in separated 2048-bytes TX/RX FIFO are used for this purpose to let user R/W the wanted payload. User can also enable additional packet features like CRC for error detection, FEC (hamming 7 by 4) for 1-bit data correction per code word, Manchester coding, as well as data whitening for data encryption / decryption.
Additional device features such as on-chip regulator, RSSI for clear channel assessment, a thermal sensor, low battery detector, carrier detect, preamble detect, frame sync in FIFO mode, auto-ack and auto-resend, AIF (Auto IF function), AFC (Auto Frequency compensation), Auto calibration (VCO, IF Filter), PLL/CLK Generator, on-chip compensated capacitors of Xtal loading, and WOR (Wake on RX) to support the ability to periodically wake up from sleep mode to RX mode and listen for incoming packets without MCU interaction, which can be used to simplify system development and cost. Overall, A9146M4’s highly integrated features and low current consumption offer a reduced BOM cost for a high performance ISM bands product. All features are integrated in a small QFN 8X8 64 pins package.
Protocol Implementation Conformance Statement (PICS): contains information such as supported data rates, frequency bands and other features